View CS98100_5001454.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CS98100 DVD Processor for Low Cost DVD Players
Features
32-Bit RISC Processor, supported by RTOS, C/C++ compilers 32-bit DSP capable of AC-3, MPEG, DTS, MP3, and WMA Progressive Scan (480p) with 3:2 pull down support or Interlaced (PAL/NTSC) video encoding, both modes with Macrovision encoding, via three 10-bit Video DACs Serial DVD data interface for direct connection to low cost (track buffer-less) DVD loader Flexible interface connects ATAPI, local bus or microcontroller-less DVD loaders without external logic MPEG decoder supports VCD, VCD 3.0, SVCD, DVD video standards Advanced subpicture unit handles DVD and SVCD, and PAL<->NTSC scaling High quality video scaling for zoom and NTSC/PAL conversion 4-bit multi-region OSD and special video effects Simultaneous 8 channels PCM audio output and IEC-958. 2-Channel PCM audio input for high-end karaoke applications Three serial control/status ports Low-power, ~0.5 W power dissipation
Description
Building on innovative, market-leading technology, Cirrus Logic presents the most complete DVD processor solution available: CS98100. The CS98100 provides the highperformance typical of Cirrus Logic integrated circuits, and on-chip integration that allows for seamless integration of functions. Among the integrated functions in this system-on-chip architecture is a high quality NTSC/PAL encoder with a triple 10-bit video DAC, allowing for a significant decrease in system cost. Not only is the CS98100 equipped with an intuitive onscreen display and user interface, but the CS98100 also offers progressive output, DTS decoding, HDCD support, and MP3 plus WMA decoding. Other advanced features include karaoke down-mix. The low cost extended feature set makes the CS98100 ideal for both low-end and high-end system manufacturers. ORDERING INFORMATION CS98100-CM 0 to 70 C 208-pin MQFP
RISC I-Cache CPU Pipe D-Cache MAC Instruction Cache
DSP X, Y Data Memory
CPU/MAC MPEG Decoder VLC Parser RAM IDCT MoCo System Controls Registers PLL Dataflow Engine DMA / BitBlit SRAM Buffer DMA #2 Memory Controller SDRAM Control FLASH Control
Audio Interface PCM Out PCM In ADC IEC-958 System Sync Interrupts STC Subpicture Decoder Decoder Scaler Video Processor On-Screen Display Video/Graphics Scaling Display NTSC/PAL Encoder 3 DACs
External Interface 2-Wire Serial 3/4 Wire Serial Programmable I/O Infrared Input DVD ATAPI/ LBUS Interface Serial DVD Interface
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved)
(c)
JUL `02 DS552PP4 1
CS98100
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 1.1 AC and DC Parametric Specifications ............................................................................... 5 1.1.1 Absolute Maximum Rating .................................................................................... 5 1.1.2 Recommended Operating Conditions ................................................................... 5 1.1.3 Electrical Characteristics ....................................................................................... 5 1.2 AC Characteristics ............................................................................................................. 7 1.2.1 ATAPI Interface ..................................................................................................... 7 1.2.2 SDRAM Interface .................................................................................................. 8 1.2.3 DVD Serial Interface Timing ................................................................................ 11 1.2.4 Digital Video Interface Timing ............................................................................. 12 1.2.5 Digital Audio Interface Timing ............................................................................. 13 1.2.6 ROM/NVRAM Interface ....................................................................................... 15 1.2.7 Miscellaneous Timings ........................................................................................ 17 2. TYPICAL APPLICATION ........................................................................................................ 18 2.1 CS98100 Device Summary ............................................................................................. 18 3. FUNCTIONAL DESCRIPTION ............................................................................................... 20 3.1 RISC Processor ............................................................................................................... 20 3.2 DSP Processor ................................................................................................................ 20 3.3 Memory Control ............................................................................................................... 20 3.4 Dataflow Control (DMA) ................................................................................................... 20 3.5 System Control Functions ................................................................................................ 20 3.6 DVD/ATAPI Interface ....................................................................................................... 21 3.7 Serial DVD Interface ........................................................................................................ 21 3.8 MPEG Video Decoding .................................................................................................... 21 3.9 Audio Processing ............................................................................................................. 21 3.10 Video Processing ........................................................................................................... 22 3.11 Video Encoder ............................................................................................................... 22 4. MEMORY MAP AND REGISTERS ......................................................................................... 23 4.1 Processor Memory Map ................................................................................................... 23
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com/en/contacts/sales.
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those components in a standard I2C system.
2
CS98100
4.2 Host Port Memory Map .................................................................................................... 23 4.3 Internal IO Space Map ..................................................................................................... 24 4.4 CS98100 Register Space ................................................................................................ 24 5. PIN DESCRIPTIONS .............................................................................................................. 37 6. PIN ASSIGNMENTS ............................................................................................................... 38 6.1 Miscellaneous Pins .......................................................................................................... 46 6.2 Serial Interface ................................................................................................................ 47 6.3 SDRAM Interface ............................................................................................................. 48 6.4 ROM/NVRAM Interface ................................................................................................... 49 6.5 Digital Video Output Interface .......................................................................................... 50 6.6 Audio Output/Input Interface ............................................................................................ 51 6.7 Host Master/ATAPI Interface ........................................................................................... 52 6.8 DVD I/O Channel Interface .............................................................................................. 53 6.9 DVD Serial Data Interface ............................................................................................... 54 6.10 Video Encoder Interface ................................................................................................ 55 6.11 General Purpose Input/Output (GPIO) .......................................................................... 56 6.12 Power and Ground ........................................................................................................ 57 7. 208 PIN MQFP PACKAGE SPECIFICATIONS ...................................................................... 58
LIST OF FIGURES
Figure 1. ATAPI Interface Timing Diagram ..................................................................................... 7 Figure 2. SDRAM Refresh Transaction........................................................................................... 8 Figure 3. SDRAM Burst Read Transaction ..................................................................................... 9 Figure 4. SDRAM Burst Write Transaction ..................................................................................... 9 Figure 5. CS98100 SDRAM Read and Write ................................................................................ 10 Figure 6. CS98100 DVD Serial Interface Timing Diagram............................................................ 11 Figure 7. CS98100 Digital Video Interface Timing Diagram ......................................................... 12 Figure 8. Digital Audio In Timing Diagram .................................................................................... 13 Figure 9. Digital Audio Out Timing Diagram.................................................................................. 14 Figure 10. ROM/NVRAM Reading Timing .................................................................................... 15 Figure 11. ROM/NVRAM Write Timing ......................................................................................... 16 Figure 12. Miscellaneous Timings................................................................................................. 17 Figure 13. CS98100 Application ................................................................................................... 18 Figure 14. CS98100 Pin Layout .................................................................................................... 37 Figure 15. CS98100 208-Pin MQFP Package Drawing ................................................................ 58
LIST OF TABLES
Table 1. ATAPI Interface Characteristics ........................................................................................ 7 Table 2. SDRAM Interface Characteristics ..................................................................................... 8 Table 3. CS98100 DVD Interface Characteristics......................................................................... 11 Table 4. CS98100 Digital Video Interface Characteristics ............................................................ 12 Table 5. Digital Audio In Characteristics ....................................................................................... 13 Table 6. Digital Audio Out Characteristics .................................................................................... 14 Table 7. RAM/NVROM Characteristics ......................................................................................... 15 Table 8. Miscellaneous Timing Characteristics............................................................................. 17 Table 9. Memory Map - RISC Processor ...................................................................................... 23 Table 10. Host Port Memory Map ................................................................................................. 23 Table 11. Internal IO Space Map .................................................................................................. 24 Table 12. CS98100 Register Map and Blocks .............................................................................. 24 Table 13. CS98100 Registers ....................................................................................................... 25
3
CS98100
Table 14. Pin Type and Direction Legend ..................................................................................... 37 Table 15. Pin Assignments............................................................................................................ 38 Table 16. Miscellaneous Interface Pins......................................................................................... 46 Table 17. Serial Interface Pin Assignments .................................................................................. 47 Table 18. SDRAM Interface Pin Assignments............................................................................... 48 Table 19. ROM/NVRAM Interface Pin Assignments ..................................................................... 49 Table 20. Video Output Interface Pin Assignments....................................................................... 50 Table 21. Audio Output Interface Pin Assignments....................................................................... 51 Table 22. Host Master Interface Pin Assignments ........................................................................ 52 Table 23. DVD I/O Channel Interface Pin Assignments ................................................................ 53 Table 24. DVD Serial Data Interface Pin Assignments ................................................................. 54 Table 25. Video Encoder Interface Pin Assignments .................................................................... 55 Table 26. General Purpose I/O Interface Pin Assignments........................................................... 56 Table 27. Power and Ground ........................................................................................................ 57
4
CS98100
1. CHARACTERISTICS AND SPECIFICATIONS
1.1 AC AND DC PARAMETRIC SPECIFICATIONS (AGND, DGND=0V, all voltages with respect to 0V)
1.1.1 ABSOLUTE MAXIMUM RATING
Symbol VDDIO VDDCORE VI II IO TSOL TVSOL TSTOR TAMB Ptotal Description Power Supply Voltage on I/O ring Power Supply Voltage on core logic and PLL Digital Input Applied Voltage (power applied) Digital Input Forced Current Digital Output Forced Current Lead Soldering Temperature Vapor Phase Soldering Temperature Storage Temperature (no power applied) Ambient Temperature (power applied) Total Power consumption -40 0 Min -0.5 -0.5 -0.5 -10 -50 Max 4.6 2.5 5.5 10 50 260 235 125 70 2 Unit Volts Volts Volts mA mA
o
C
oC o
C
oC
W
CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to the device. Cirrus Logic recommends that CS98000 devices operate at the settings described in the next table.
1.1.2
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VDD VDD TAMB Min 3.0 1.62 0 Typ 3.3 1.8 25 Max 3.6 1.98 70 Units Volts Volts
oC
Supply Voltage, IO Supply Voltage, core and PLL Ambient Temperature (power applied)
1.1.3
ELECTRICAL CHARACTERISTICS
Parameter Power Supply Supply Voltage, IO Supply Voltage, core and PLL Supply Current, IO Supply Current, core and PLL Digital Pins Input Voltage, High Input Voltage, Low Symbol VDD VDD IDD IDD VIH VIL Normal Operating Normal Operating 2.2 0.8 Conditions Min 3.0 1.62 Typ 3.3 1.8 45 210 Max 3.6 1.98 Units Volts Volts mA mA Volts Volts
5
CS98100
Parameter Input Current Input Pull up/down resistor Output Voltage, High Output Voltage, Low High-Z-state Leakage Analog Video Pins Full Scale Current Output Voltage Range DAC to DAC Output Voltage Range Differential Gain Differential Phase Signal to Noise Chrominance AM Noise Chrominance PM Noise 1.Only applies each set of three. matching1 Symbol IIN RI VOH VOL IOZ IFS VIO MAT Vout DG DP SNR AM PM RL= 37.5 1 0.5 74 80 75 @ buffer rating @ buffer rating VOUT = VSS or VDD RL = 37.5 RL = 37.5 -1 34 1.28 2 1.28 2.4 0.4 +1 Conditions VIN = VDD or VSS Min -1 75 Typ Max +1 Units A K Volts Volts A mA Volts % Volts % deg dB dB dB
6
CS98100
1.2 AC CHARACTERISTICS (TA= 25C; VDD_PLL=VDD_CORE=1.8 V10%, VDD_IO=3.3 V10%)
1.2.1 ATAPI Interface
The CS98100 can interface with ATAPI-type slave loader gluelessly. Figure 1 illustrates a read ATAPI transaction and a write ATAPI transaction. PIO mode 4 is implemented for sufficient data transfer rate between ATAPI device and the CS98100. See Table 1 for the ATAPI symbols and characterization data.
Symbol
tacyc1 t t
Description Cycle Time Address Valid to HMRD-/HMWR- Setup 7
Min 87
Typ
Max
Unit ns ns ns ns ns ns ns ns ns
aavr ah
Address Hold from HMRD-/HMWR Setup 8 H_RD/H_WR Pulse Width H_RD/H_WR Recovery Time H_WR Data Setup H_WR Data Hold H_RD Data Setup H_RD Data hold H_RD Data three-state H_RDY Setup Time H_RDY Hold Time 0 58 19 20 4 20 0 7 14
tarww t
arec
tawsu t t
awh ardsu
tarddh t
ardts arh1
ns ns ns
tarsu t
Table 1. ATAPI Interface Characteristics 1.Values are guaranteed by design only
H_A[2:0] , H_CS[3:0] t aavr H_RD/H_WR t arww t
ah
tacyc
tarec
H_D[15:0](WRITE) tawsu H_D[15:0](READ) tarsu H_RDY(deasserted before tarsu) t arh H_RDY(asserted before tarsu) tardsu t arddh tardts tawh
Figure 1. ATAPI Interface Timing Diagram
7
CS98100
1.2.2 SDRAM Interface
The CS98100 interfaces with either SDRAM or SGRAM, for high data bandwidth transfer. Figure 5 and Table 2 show the interface pin timing. Figure 2 shows the refresh cycle performed by the CS98100. Figure 3 shows a burst read (length = 8) transaction, while Figure 4 shows a burst write (length=8) transaction. In both Figure 3 and Figure 4, CAS latency is programmed to 3.
Symbol
tmco t
Description Output Delay from DR_CKO active edge DR_CKO Period DR_D[31:0] delay from DR_CKO DR_D[31:0] valid time after DR_CKO DR_D[31:0] setup to DR_CKO
Min 11
Typ 9 12.2
Max
Unit ns ns
mper
tmdow t t
9.1 1.5 3.9
ns ns ns ns ns ns
mhw msur1 mhr1
tmsurd1 t
DR_D[31:0] setup to DR_CKO with delay 4.3 DR_D[31:0] hold time after DR_CKO 1.85
tmhrd1
DR_D[31:0] hold time after DR_CKO with 1.3 delay Table 2. SDRAM Interface Characteristics
1.Delay is programmable by selecting the DRAM_Input_Speed bit of the Command Register(0x000)
DR_CKO DR_A[11:0] DR_BS_N DR_RAS_N DR_CAS_N DR_WE_N DR_D[31:0] DR_DQM_[3:0] DR_AP
Figure 2. SDRAM Refresh Transaction
8
CS98100
DR_CKO DR_A_[11:0] DR_CKE DR_RAS_N DR_CAS_N DR_WE_N DR_D[31:0] DR_DQM[3:0] F D0 0 D1 D2 D3 D4 D5 D6 F D7 R0 C0 C1 C2 C3 C4 C5 C6 C7
Figure 3. SDRAM Burst Read Transaction
DR_CKO DR_A_[11:0] DR_CKE DR_RAS_N DR_CAS_N DR_WE_N DR_D[31:0] DR_DQM[3:0] F D0 D1 D2 D3 0 D4 D5 D6 D7 F R0 C0 C1 C2 C3 C4 C5 C6 C7
Figure 4. SDRAM Burst Write Transaction
9
CS98100
tmco DR_CKO DR_RAS_N,DR_CAS_N DR_W E_N,DR_AP,DR_DQM[3:0], DR_CKE,DR_A[11:0] DR_D[31:0](WRITE)
tmper
tmdow
tmhw
DR_D[31:0](READ) tmsur tmhr
Figure 5. CS98100 SDRAM Read and Write
10
CS98100
1.2.3 DVD Serial Interface Timing
Figure 6 and Table 3 illustrate the signal timing for the DVD serial interface input pins.
Symbol
t
Description DVDS_CLK Period DVDS_CLK Low Time DVDS_CLK High Time DVDS_DATA Setup to DVDS_CLK active edge
Min 33 40 40 4
Typ 50 50
Max
Unit ns % % ns ns ns ns
dsckper dsckh1 dsdsu dsdhd dscdsu
1
tdsckl1 t t t t
DVDS_DATA Hold after DVDS_CLK active edge 0 DVDS_VLD,DVDS_SOS Setup to DVDS_CLK 3
tdscdhd
DVDS_VLD,DVDS_SOS Hold after DVDS_CLK 0 Table 3. CS98100 DVD Interface Characteristics
1.Values are guaranteed by design only
t dsckper
DVDS_CLK (Input)
tdsckl
t dsckh t dsdsu t dsdhd
DVDS_DATA (Input)
t dscdsu
DVDS_VLD, DVDS_SOS (Input)
t dscdhd
Figure 6. CS98100 DVD Serial Interface Timing Diagram
11
CS98100
1.2.4 Digital Video Interface Timing
Figure 7 illustrates the signal timing for the digital video interface pins. The clock is without a polarity to show the clock may be inverted by register programming. This also illustrates that data is clocked out on both clock edges in progressive mode. The data order is Cr,Y0,Cb,Y1, and the sync outputs may be programmed as active high or active low.
Symbol
tvocper1 t
Description CLK27_O period VDAT[7:0] delay from CLK27_O Vsync/Hsync delay from CLK27_O
Min -10 -10
Typ 37.037
Max 10 10
Unit ns ns ns
covo12
tcovo22
Table 4. CS98100 Digital Video Interface Characteristics 1.Values are guaranteed by design only 2.It is recommanded that the output data should be taken at the opposite edge of the CLK27_O.
Tvocper
CLK27_O (Output)
Tcovo1 VDAT[7:0] (Output) Tcovo2
VSYNC/HSYNC (Output)
Figure 7. CS98100 Digital Video Interface Timing Diagram
12
CS98100
1.2.5 Digital Audio Interface Timing
Figure 8 and Figure 9 illustrate the signal timing for the digital audio pins. The bi-directional AUD_XCK pin clocks at 8x the frequency of the AUD_BCK pin. The AUD_BCK pin outputs at 32x or 48x of the sample frequency, and transitions on the falling edge of the AUD_XCK pin. AUD_BCK is shown without polarity to indicate the polarity is programmable.
Symbol
tslri t
Description AIN_LRCK setup to AUD_BCK active edge AIN_DATA setup to AUD_BCK active edge
Min 25 25
Typ -
Max
Unit ns ns ns
sdi
thsdi
AIN_DATA hold time after AUD_BCK active edge 1 Table 5. Digital Audio In Characteristics
*AUD_BCK (Output) t lrts AIN_LRCK (Input) t sdsus t sdhs AIN_DATA (Input) * Active clock edge is programmable. Timing is referenced from active edge.
Figure 8. Digital Audio In Timing Diagram
13
CS98100
Symbol
taxch1
Description
Min
Typ 50 50
Max
Unit % % ns
AUD_XCLK High Time (AUD_XCLK is Input/Output) 40 AUD_XCLK Low Time (AUD_XCLK is Input/Output) 40 AUD_XCLK period (Input/Output) AUD_BCK delay from AUD_XCLK(output) active edge AUD_BCK delay from AUD_XCLK(input) active edge AUD_BCK period AUD_LRCK delay from AUD_BCK active edge AUD_D[3:0] delay from AUD_BCK active edge 216 -10 -10 27
taxcl1
t
axper
todbck t
10 21
ns ns ns
odbck
taoper t
odlr2
10 10
ns ns
todsd2
Table 6. Digital Audio Out Characteristics 1.Values are guaranteed by design only 2.It is recommanded that the output data should be taken at the opposite edge of the AUD_BCK.
t AUD_XCLK(Input/Output) t AUD_BCK(Output) t
axcl
axper
t
axch
odbck
t aoper
* AUD_BCK(Output)
t odlr AUD_LRCK(Output) t odsd AUD_DO[3:0] (Output) * Active clock edge is programmable. Timing is referenced from active edge.
Figure 9. Digital Audio Out Timing Diagram
14
CS98100
1.2.6 ROM/NVRAM Interface Symbol
trc t t
Description Read Cycle Time CE to Data Setup OE to Data Setup Address to Data Setup Address to WE setup (Write) CE to WE setup (Write) WE Pulse Width (Write) CE to Data Output (Write) WE to Data Hold (Write)
Min 98
Typ
Max 80 70 90
Unit ns ns ns ns ns ns ns
cds ods
tads t
aws
20 5 160 -5 10
tcws t t
wp wdo
ns ns
tdh
Table 7. RAM/NVROM Characteristics Note:Read timing based on 10.5 ns memory clock and 4 programmed wait states.
t rc
A d d re ss M _ A [11 :0 ], M _ D [27 :1 6] N V M _ C E _N
t cds
NVM_OE_N (M _A P )
t ods
tads
M _D [7 :0 ]
NVM_W E_N
Figure 10. ROM/NVRAM Reading Timing
15
CS98100
t aw s
A dd re ss M _A [1 1:0 ], M _D [2 7:1 6] N V M _C E _ N
tc w s
N V M _W E _ N
tw p
t w do
M _D [7 :0] N V M _O E _ N (M _ A P )
t w dh
Figure 11. ROM/NVRAM Write Timing
16
CS98100
1.2.7 Miscellaneous Timings
Symbol txclper trstl tgph tgpl
1
Description XTLCLK period RST_N Low Pulse Width GPIO PW High GPIO PW Low
Min 1000 50 50
Typ 37.037
Max
Unit ns ns ns ns
Table 8. Miscellaneous Timing Characteristics 1.XTLCLK must meet the requirement of external the video encoder for correct chroma (27 MHz 1 KHz).
t xccper
XT L CL O C K trstl RESET-N tgph tgpl
GPIO
Figure 12. Miscellaneous Timings
17
CS98100
2. TYPICAL APPLICATION
Figure 13 shows an example of a complete high-end DVD solution using the CS98100.
Front Panel
27M XTAL (4)Audio DACs
Audio
IR
Audio ADC
AudioUp to 8 Channels S/PDIF Composite Video S-Video
CS98100
DVD Loader (IO Channel, ATPAI or Serial)
1/ -1MB 2
ROM/ FLASH
SDRAM 4-8MB Power Reg.
Component Video Switch Power
Figure 13. CS98100 Application
2.1 * * * * * * * * * * * * *
18
CS98100 Device Summary
RISC-32
Powerful 32-bit RISC processor Optimizing C compiler and source level debugger Big or little endian data formats supported MAC multiply/accumulate in two cycles with C support. 4 Kbyte instruction cache, 2 Kbyte data cache. Single cycle instructions run at 90 MHz.
DSP-32
* * * * * * * *
Powerful 24/32-bit DSP processor 24-bit fixed point logic, with 54-bit accumulator. Single-cycle throughput, 2-cycle latency multiply accumulate, 32-bit simple integer logic. 8 Kbyte instruction cache, 12 Kbyte program visible local memory Single cycle instructions run at 90 MHz.
SYSTEM CONTROLS
communication 32-bit timers for I/O and other uses, with programmable interval rates Both hardware and software interrupts on data or debug Performance monitors which measures DRAM bandwidth, usage, and RSK performance Built in PLLs generate all required clocks from 27 MHz input clock. Memory Controller Supports SDRAM, and SGRAM, from 2 MBytes to 32 MBytes. Supports multiple banks of FLASH and ROM up to 32 MBytes. 32-bit data bus for DRAM, 8 or 16-bit data bus for ROM.
DATA FLOW ENGINE
* * *
Include several hardware lockable semaphore registers General-purpose registers for inter-processor
Two DMA controllers - local memory based and direct memory-to-memory 2432 bytes of internal memory, DMA to/from main RAM into local SRAM. Supports endian conversion and byte, short,
CS98100
long data formats on DMA. Supports block transfers for graphics bit blits.
MPEG VIDEO DECODER
* *
* * * * * * * *
Supports VCD1.0, 1.1, 2.0 and 3.0, SVCD, and DVD video standards. Supports trick features, including smooth 2x forward play. Special anti-tearing logic controls picture decode and presentation. Advanced error concealment hardware.
SYSTEM SYNCHRONIZATION
IO channel interface supports standard DVD loader protocols Separate serial DVD interface to support lowcost (track buffer-less) loaders
VIDEO PROCESSOR
*
*
System time clock (STC) for audio/video synchronization Flexible interrupt structure for controlling decode and presentation times Hardware scheduling of sub-picture and highlight events
AUDIO INTERFACE
*
* * *
On screen display module supports 2-bit or 4bit, pixel modes. It supports 3 separate regions and 16 transparency overlay levels High quality scaling using 16 tap polyphase programmable vertical and horizontal filters, to support any size image up to 768x576. Multiple video plain overlays (main video / subpicture / picture-in-picture / on-screen display). Gamma Correction. Progressive scan video output
VIDEO ENCODER
* * *
Supports 8 channels PCM, I S at up to 24 bits and 96 kHz output rate. Simultaneous IEC-958 output with programmable channel status and user data Also supports S/PDIF receiver for high performance applications
EXTERNAL INTERFACE
2
* * * * * * * * * * * * * *
* * * * * *
*
2-wire serial master and slave port, second 2wire master port for controlling DVD device. 3- or 4-wire serial master/slave port. Large number of programmable bi-directional I/O pins. All pins not used for other function can be reassigned as general purpose I/O pins 8 pins can be used as edge or level detection interrupt pins. Hardware-assisted support for infrared remote devices, such as remote control, infrared keyboard, mouse, printer, and more. Programmable parallel host master interface supports formats including ATAPI, ISA, and more.
Three 10-bit video DACs, drive 37.5 load directly without external buffering Supports PAL (B,D,G,H,I,N) and NTSC Component (RBG or YUV) or composite + SVideo output Progressive or interlaced mode output Macrovision 7.1 support (interlaced) and Macrovision 1.03 support (progressive) Wide-screen signaling support (interlaced and progressive) and CGMS support Closed captioning support
SUB-PICTURE PROCESSOR
Run-length decode DVD sub-pictures and SVCD OGT formats Hardware vertical scaling supports NTSC-PAL format conversion 16 level alpha blending System Functions 208-pin MQFP package. All I/O pins are 3V with 5V tolerance. Advanced 0.18 micron CMOS technology. Chip runs at 90 MHz Supports Low power modes and clock shutoff.
19
CS98100
3. FUNCTIONAL DESCRIPTION
3.1 RISC Processor The CS98100 includes a powerful, proprietary 32bit RISC processor with optimizing C compiler support. The RISC has a MIPS-compatible instruction set, as well as a MAC engine which performs multiply/accumulate in 2 cycles in a pipelined fashion with C support, effectively achieving single cycle throughout. The CS98100 fully supports many Real Time Operating Systems (RTOS). The RISC processor co-ordinates on-chip multi-threaded tasks, as well as supervises system activities such as remote control and VFD front panel control. 3.2 DSP Processor The CS98100 contains a proprietary digital signal processor (DSP) which is optimized for audio applications. The DSP performs 32-bit simple integer operations, and has a 24-bit fixed point logic unit, with a 54-bit accumulator. There are 32 generalpurpose registers, and eight independent address generation registers, featuring: post-increment ALU, linear and circular buffer operations, bit reverse ALU operations, and dual operand read from memory. The multiply-accumulator has single-cycle throughput, with two cycle latency. The DSP is optimized for bit packing and unpacking operations. The interface to main memory is designed for bursting flexible block sizes and skip counts. 3.3 Memory Control The DRAM Interface performs the SDRAM control and arbitration functions for all the other modules in the CS98100. The DRAM interface services and arbitrates a number of clients and stores their code and/or data within the local memory. This arbitration and scheduling guarantees the allocation of sufficient bandwidth to the various clients. The DRAM Interface supports up to 32 MByte. For a typical DVD player application, CS98100 requires 8 MByte of SDRAM and 1 MByte of FLASH. Sharing the same interface, the CS98100 also supports flash ROM, OTP, or masked ROM interface. Code is stored in ROM. After the system is booted, the code is shadowed inside DRAM for execution. FLASH ROM interface is provided so that the code can be upgraded in field once the communication channel is established via, for example, CD-R or serial port. Utility software will be provided to debug and upgrade code for the system manufacturer. 3.4 Dataflow Control (DMA) The DMA controller moves data between the external memory and an internal memory. The external memory address can be specified using a register, or in FIFO mode, using start and end address registers. Separate start/end address registers are used for DMA read and write operations. The DMA interface also has a block transfer function, which allows for the transfer of one block of data from one external memory location to another external memory location. In effect, combining a DMA read and write into one operation. In addition, the DMA write operation allows for byte, short, word, and other types of masking. A second dedicated DMA controller provides for fast memory-to-memory transfers. 3.5 System Control Functions The system control functions are used to coordinate the activities of the multiple processors, and to provide the supporting system operations. Four 32-bit communication registers are available inter-processor communication, and eight semaphore registers are used for resource locking. Timers are available for general-purpose functions, as well as more specialized functions such as watchdog timers and performance monitoring. The large number of general purpose I/Os offers flexibility in system configurations. Three separate serial interfaces, conforming to industry-standard protocols, are available for a vari-
20
CS98100
ety of system interface functions. Interrupts can be generated on specific or generic events. Infrared inputs can be filtered of glitches or stored unfiltered into memory. Power-down control of the internal clocks is also possible. Internal PLLs are used to generate the internal system and memory clocks, and audio clocks of any widely used frequency. 3.6 DVD/ATAPI Interface The CS98100 has a programmable interface port, which can be configured to connect to industry standard CD/DVD loaders without external glue logic. The CD/DVD interface fully supports a wide range of popular CD/DVD loaders. The interface consists of DVD control and data ports, and an optional CD control/data port. The CS98100 hardware manages the DVD interface and moving data to an arbitrary size input FIFO in DRAM. The same interface pins can be optionally configured as a generic 16-bit host master port. In this mode, the CS98100 can control up to four devices (using 4 chip select outputs), each of which may use different protocol and timing. The interface can be set up in ATAPI mode, to connect directly to any ATAPI DVD loader (using two chip selects). Simultaneously, the other two chip selects can be configured to connect to other devices, such as a super I/O chip or hard disk. A third option is to configure the interface for micro-less DVD loader operation, which may also be configured to connect without external glue logic. 3.7 Serial DVD Interface The CS98100 has a 4-pin serial port which interfaces to the data port of popular low-cost DVD loaders. This type of loader provides for low system cost by eliminating the track buffer, interface FIFO, and flow control logic. The CS98100 contains a large internal SRAM to handle high burst data rates, without requiring reverse flow control. The track buffer resides in the CS98100 SDRAM, which reduces system complexity and simplifies the software architecture. The CS98100 performs error detection, sector number tracking, and interrupt generation. 3.8 MPEG Video Decoding Compressed MPEG data is read from the DVD disk into an input FIFO in DRAM. The data flow (DMA) controller moves Video packets from the input FIFO into the MPEG decoder's input FIFO (also in DRAM). The DMA controller can also perform advanced functions such as start code search, relieving the RISC processor. The System Sync function is used to control the timing of MPEG picture decoding. The MPEG Video decoder processes I, B and P frames, and writes to video frame buffers in DRAM, for output to the display. Special anti-tearing logic ensures currently displayed frame buffers are not overwritten. 3.9 Audio Processing Compressed Audio data is read from the DVD disk into an input FIFO in DRAM. The data is decompressed, then written to a PCM output FIFO, also in DRAM. Presentation time stamps (PTS) are extracted from the stream to update the STC, in order to maintain audio/video synchronization. The DMA and decompression stages of audio processing can be done with a combination of the DMA unit, DSP and RISC processors. The DSP is optimized for audio processing, so most common formats can be handled by the DSP alone, including AC-3, MPEG2 audio, and others. The DSP has enough reserve bandwidth to handle the Karaoke echo-mix and pitch shift, and AC-3 down-mix functions. The audio output data is written into a DRAM FIFO in 16, 18, 20 or 24-bit PCM format. A flexible audio output stage can simultaneously output 8 channels of PCM data to audio DACs, plus an IEC958 encoded output, at up to 96 kHz. The IEC-958 output has fully programmable channel status (commercial), and provides a flexible solution to support all IEC-958 modes for User Data.
21
CS98100
The audio interface also includes a flexible PCM input interface, which can input a wide range of protocols from IEC-958 receiver. Another, lowcost approach for audio input is the internal sigmadelta demodulator. This module inputs a digital PWM version of the audio input, which can be created on the board using an inexpensive ramp generator and comparator. The sigma-delta demodulator uses a set of programmable filters to reconstruct 9bit (mono) audio data at up to 12 kHz sampling frequency. 3.10 Video Processing The CS98100 Video processor is a powerful, fully programmable video post processing engine that displays video on an interlaced TV or a progressive HDTV. A 16-tap polyphase vertical filter is fully programmable on a line-by-line basis, to provide high quality vertical scaling and interlaced field conversion. Horizontal filtering is done with a programmable 16-tap polyphase filter. This advanced filter processing is used for de-interlacing, zoom, and frame size conversion. Source mode of interlaced or progressive is determined from the disk type automatically. For progressive source detection, 3:2 pulldown is detected from status flags in the video stream to ensure optimized playback. Interlaced video source is filtered up to progressive size output using the bilinear vertical filter. This is visibly superior to simple line doubling. Each 240 line field being filtered and output at 480p. Progressive video source is output at the full progressive resolution. Each 480 line frame output at 480p. Source mode of interlaced or progressive is determined from the disk type. For progressive source detection, 3:2 pulldown is simply detected from status flags in the video stream. Zoom is fully programmable, from 1X to 500X zoom, with any value in between. Frame type conversion, from NTSC to PAL, or PAL to NTSC, is done with a the bilinear vertical filter, reducing flicker and jaggies. There is a programmable gamma-correction lookup table for the final output. Cirrus Logic provides some easy to use utilities in order to get the best advantage of the powerful video filtering capabilities of the CS98100. The video encoder sends progressive or interlaced digital video data to the internal video encoder, and can output parallel digital data to an external video encoder. The video processor also allows multiple video plain overlay (main video / sub-picture / on-screen display). The sub-picture unit is a hardware-only solution which performs high-quality vertical scaling for PAL/NTSC conversion, and full support for DVD (sub-picture) and SVCD (OGT) modes. The on-screen display unit features 2-bit and 4-bit pixels, 16 transparency levels, and three independent regions of up to full-screen size. The picture-in-picture unit can place a 1/2 or 1/4 screen sized window anywhere on the screen. This feature can be used for special effects, such as snapshot freeze and zoom assist. 3.11 Video Encoder The video encoder uses three 10-bit DACS to convert digital data to component (RGB or YPRPB) or composite (composite plus S-Video) analog video. The output can be interlaced (PAL/NTSC) or high resolution progressive. In progressive mode, the video encoder will typically drive YPRPB to a 525line television at 59.94 Hz, although other output modes are possible, such as 625 lines and RGB. The encoder performs the Macrovision copy protection function for all modes (revision 7.1 for interlaced, revision 1.03 for progressive). Other features include built-in voltage reference, color bar generator, individual power-down control for each DAC, programmable baseband filters, color/contrast/tint controls, Closed Captioning (interlaced modes), wide screen signalling (PAL mode), and Copy Generation Management System (NTSC and progressive modes).
22
CS98100
4. MEMORY MAP AND REGISTERS
4.1 Processor Memory Map The CS98100 externally supports up to 32 Mbytes DRAM and 16 Mbytes ROM/NVRAM. Table 9 lists the memory map as viewed by the RISC processor, and identifies whether each segment is mapped or cacheable.
Processor byte address 0000_0000 - 07FF_FFFF 8000_0000 - 81FF_FFFF 9400_0000 - 9CFF_FFFF 9C00_0000 - 9CFF_FFFF 9D00_0000 - 9DFF_FFFF A000_0000 - A1FF_FFFF B000_0000 - B003_FFFF B400_0000 - BCFF_FFFF BC00_0000 - BCFF_FFFF BD00_0000 - BDFF_FFFF C000_0000 - FFFF_FFFF
Description DRAM (mapped) DRAM (32 Mbytes) 16 bit NVRAM write (16 Mbytes) 16 bit NVRAM/ROM (16 Mbytes) 8 bit NVRAM/ROM (16 Mbytes) DRAM (32 Mbytes) Internal I/O (256 Kbytes) 16 bit NVRAM write (16 Mbytes) 16 bit NVRAM/ROM (16 Mbytes) 8 bit NVRAM/ROM (16 Mbytes) DRAM (mapped)
Cacheable Y Y N Y Y N N N N N Y
Table 9. Memory Map - RISC Processor
4.2 Host Port Memory Map Table 10 lists the memory map as viewed by host slave port.
Host byte address 0000 0000 - 003F FFFF 1000 0000 - 13FF FFFF 1400 0000 - 17FF FFFF
Description Internal I/O Space DRAM space (16 Mbytes) NVRAM space (16 Mbytes) Table 10. Host Port Memory Map
23
CS98100
4.3 Internal IO Space Map Table 11 shows how the Internal IO space is mapped between general registers, internal SRAM ports, and the RISC processor debug port.
Byte address offset 0_0000 - 0_2FFF 0_3000 - 1_FFFF 2_0000 - 2_FFFF
Description General registers General Internal SRAM RISC Internal SRAM/Registers
Table 11. Internal IO Space Map
4.4 CS98100 Register Space Table 12 lists the register groups, and how they are split among the main CS98100 functional blocks.
CS98100 Register 000xx, 010xx 001xx 002xx 003xx 004xx 005xx 006xx 007xx 008xx 00Axx 00Bxx 00Cxx 00Dxx 00Exx 02xxxx
Block General Host DRAM Controller (DRC) DMA CD/DVD Interface Serial DVD (DVDS) DSP Sync Control MPEG Video Decoder Picture-in-picture Video Processor Subpicture Display On-screen Display PCM In/Out RISC Processor
Table 12. CS98100 Register Map and Blocks
Table 13 lists all the registers for the CS98100 and their addresses, and indicates whether the registers are read/write (R/W), read only (RO) or write only (WO).
24
CS98100
Address 0 10 14 18 10C 20 24 28 02C 30 34 38 03C 40 44 48 04C 50 54 58 05C 60 1040 1044 1048 1064 1068 106C
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W RO R/W
Function General General General General General General General General General General General General General General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) Table 13. CS98100 Registers
Register Name Command InterProc_Comm_Register_0 InterProc_Comm_Register_1 InterProc_Comm_Register_2 InterProc_Comm_Register_3 Semaphore_Register_0 Semaphore_Register_1 Semaphore_Register_2 Semaphore_Register_3 Semaphore_Register_4 Semaphore_Register_5 Semaphore_Register_6 Semaphore_Register_7 GenIO_Read_Data GenIO_Write_Data GenIO_Three_State_Enable GenIO_Positive_Edge GenIO_Negative_Edge GenIO_Interrupt_Status GenIO_Positive_Edge_Mask GenIO_Negative_Edge_Mask GenIO_Level_Mask GenIO2_Read_Data GenIO2_Write_Data GenIO2_Three_State_Enable GenIO2_Mode GenIODVD_Read_Data GenIODVD_Write_Data
25
CS98100
Address 1070 1074 68 06C 70 74 78 07C 80 84 88 08C 90 94 98 09C 0A0 0A4 0A8 0AC 0B0 0B4 0B8 0BC 0C0 0C4 0C8 0CC 0D0 0D4 Type R/W R/W R/W R/W R/W R/W RO RO R/W WO R/W RO R/W WO R/W RO R/W WO R/W RO R/W WO R/W RO R/W R/W R/W R/W R/W RO Function General (Genio) General (Genio) General (Serial IF1) General (Serial IF1) General (Serial IF1) General (Serial IF1) General (Serial IF1) General (Serial IF1) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Timer) General (Timer) General (Timer) General (Timer) General (Timer) General (Timer) Register Name GenIODVD_Three_State_Enable GenIODVD_Mode Ser1_Mstr_Byte_Read_Subaddress_Write Ser1_Mstr_Write_1Byte Ser1_Mstr_Write_2Bytes Ser1_Mstr_Control Ser1_Mstr_Status Ser1_Mstr_Read_Data RSK_Interrupt_Mask RSK_Interrupt_Set RSK_Interrupt_Status RSK_Interrupt_Cause DSP_Interrupt_Mask DSP_Interrupt_Set DSP_Interrupt_Status DSP_Interrupt_Cause RSK_Interrupt_Mask2 RSK_Interrupt_Set2 RSK_Interrupt2_Status RSK_Interrupt_Cause2 DSP_Interrupt_Mask2 DSP_Interrupt_Set2 DSP_Interrupt2_Status DSP_Interrupt_Cause2 Timer_0 Timer_1 Timer_2 Timer_3 Timer_Control Performance_Monitor_Count
Table 13. CS98100 Registers (Continued) 26
CS98100
Address 0D8 0DC 0E0 0E4 0E8 0EC 0F0 10F0 0F4 0F8 10F8 0FC 1000 1004 1008 10B0 10B4 10B8 10BC 10C0 10C4 10C8 10CC 10D0 10D4 10E0 10E4 10E8 100 104 Type R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO R/W R/W R/W R/W RO R/W R/W Function General (Timer) General (IR) General (IR) General (IR) General (IR) General (IR) General (PLL) General (PLL) General (PLL) General (PLL) General (PLL) General (PLL) General (DMA) General (DMA) General (DMA) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF3) General (Serial IF3) Host Host Register Name Timer_M_Over_N IR_Glitch_Max IR_Control IR_Dram_Start_Address IR_Dram_End_Address IR_Dram_Write_Address PLL_Control_Register1 Low_Power_Clock_Control PLL_Control_Register2 PLL_Turn_Off PLL_Monitor PLL_Clock_Divider DMA2_Source_Addr DMA2_Dest_Addr DMA2_Size Ser2_Mstr_Write_Data_0 Ser2_Mstr_Write_Data_1 Ser2_Mstr_Write_Data_2 Ser2_Mstr_Write_Data_3 Ser2_Mstr_Read_Data_0 Ser2_Mstr_Read_Data_1 Ser2_Mstr_Read_Data_2 Ser2_Mstr_Read_Data_3 Ser2_Mstr_Setup Ser2_Mstr_Command_Status Ser3_Control Ser3_Write_Data Ser3_Read_Data Device_1_Control Device_2_Control
Table 13. CS98100 Registers (Continued) 27
CS98100
Address 108 10C 110 114 120 124 128 12C 134 13C 200 204 208 20C 210 214 218 21C 220-224 300 304 308 30C 310 314 318 31C 328 32C 330 Type R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W WO R/W RO R/W R/W R/W R/W R/W R/W RO R/W Function Host Host Host Host Host Host Host Host General Host Dram controller Dram controller Dram controller Dram controller Dram controller Dram controller Dram controller Dram controller Dram controller DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA Register Name Device_3_Control Device_4_Control Write_Data_Port Read_Data_Port Host_Start_Address Dram Start Address Stream_Transfer_Size DRAM_Burst_Threshold Ser1_Slave_Address Host_Master_Control DRAM_Controller_Priority0 DRAM_Controller_Priority1 DRAM_Controller_Priority2 DRAM_Controller_Priority3 DRAM_Controller_Priority4 DRAM_Controller_Setup DRAM_Command DRAM_Controller_Mb_Width DRAM_Controller_Debug DMA_Enable DMA_Control DMA_Status Xfer_Byte_Cnt Dram_Byte_Start_Addr Sram_Byte_Start_Addr Fifo_Start_Rd_Addr Fifo_Start_Wr_Addr Search_Control Search_Status Fifo_End_Rd_Addr
Table 13. CS98100 Registers (Continued) 28
CS98100
Address 334 338 33C 400 404 408 40C 410 414 418 41C 438 440 444 448 44C 450 454 458 45C 500 504 508 510 514 518 534 53C 544 548 Type R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W RO R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W RO RO RO R/W R/W Function DMA DMA DMA CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD DVDS DVDS DVDS DVDS DVDS DVDS DVDS DVDS DVDS DVDS Table 13. CS98100 Registers (Continued) 29 Register Name Fifo_End_Wr_Addr Lines_and_Skip Mask_Pattern_Match DVD_Control DVD_Fifo_Base_Address DVD_Fifo_Size DVD_Sector DVD_Start_of_Sector DVD_Current_Dram_Address CD_Control CD_Error_Status DVD_Status DCI_Control_Reg DCI_Status DCI_Dram_Rd_Start_Addr DCI_Dram_Wr_Start_Addr DCI_Mbytes_Sent DCI_Mbytes_Switch DCI_Diagnostic DCI_Active DVDS_Control DVDS_DataSwap _Mode DVDS_Flow_Control_Ref Track_Buffer_Base Track_Buffer_End Track_Buffer_Current_Address DVDS_Sector_ID DVDS_Bad_Sector_ID Interrupt_Status Interrupt_Enable
CS98100
Address 54C 550 600 604 6XX 700 704 708 70C 710 714 718 71C 720 724 728 72C 730 734 738 73C 740 744 748 74C 750 754 758 75C 760 Type R/W R/W WO WO RO R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W RO R/W R/W R/W RW R/W R/W RO RO RO Function DVDS DVDS DSP DSP DSP Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Register Name DRAM_Underflow_Status Input_Data_Counter DSP_Boot_Code_Start_Address DSP_Run_Enable DSP_Program_CntRun_Status Audio_Sync_Control Video_Sync_Control Video_Sync_Status Wait_Line Frame_Period STC_Interval System_Time_Clock Top_Bits Video_PTS_FIFO_Start_Address Video_PTS_FIFO_End_Address Video_PTS_FIFO_Write_Address Video_PTS_FIFO_Read_Address Subpicture_PTS_FIFO_Start_Address Subpicture_PTS_FIFO_End_Address Subpicture_PTS_FIFO_Write_Address Subpicture_PTS_FIFO_Read_Address Highlight_Start_PTS Highlight_End_PTS Button_End_PTS Highlight_Control_Information_Address Video_PTS Audio_PTS Subpicture_PTS Audio_Time Video_Sync_Debug
Table 13. CS98100 Registers (Continued) 30
CS98100
Address 764 768 76C 770 774 778 77C 800 804 808 80C 810 814 818 81C 820 824 828 82C 830 834 83C 840 844 848 84C 854 858 A00 A04 Type R/W R/W R/W RO R/W WO WO R/W R/W R/W R/W RO RO WO RO R/W RO RO R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W Function Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid Decoder MPEG Vid Decoder MPEG Vid Decoder MPEG Vid Decoder MPEG Vid Decoder MPEG Vid Decoder MPEG Vid Decoder PIP PIP Register Name SP_DRC_VPTS_Debug Frame_Count_Interrupt Video_DTS Sync_Interrupt_Status Sync_Interrupt_Control Sync_Interrupt_Set Sync_Interrupt_Clear MPEG_Video_Control MPEG_Video_Setup MPEG_Video_FIFO_Start_Address MPEG_Video_FIFO_End_Address MPEG_Video_FIFO_Current_Address MPEG_Video_Horiz_Pan_Vector MPEG_Video_FIFO_Add_Bytes MPEG_Video_FIFO_Curr_Bytes MPEG_Video_FIFO_Interrupt_Bytes MPEG_Video_FIFO_Total_Bytes MPEG_Video_Status Macroblock Width_Height MPEG_Video_Debug MPEG_U_Offset MPEG_I_Base_Register MPEG_P_Base_Register MPEG_Dest_Control MPEG_Software_Flags MPEG_V_Offset MPEG_AntiTearWindow MPEG_Error_Pos PIP_Control PIP_VidBrdStartX
Table 13. CS98100 Registers (Continued) 31
CS98100
Address A08 A0C A10 A14 A18 A1C A20 A24 A28 A2C A30 A34 B00 B04 B08 B0C B10 B14 B18 B1C B20 B24 B28 B2C B30 B34 B38 B3C B40 B44 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W WO Function PIP PIP PIP PIP PIP PIP PIP PIP PIP PIP PIP PIP Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Table 13. CS98100 Registers (Continued) 32 Register Name PIP_VidBrdEndX PIP_VidBrdStartY PIP_VidBrdEndY PIP_BorderClr PIP_Vscale PIP_Line_Offnum_Bot PIP_FrBaseY PIP_FrBaseU PIP_FrBaseV PIP_Line_Width PIP_ Line_Offnum_Top PIP_Frame_Size Video_Processor_Control Video_DRAM_Line_Length Display_ActiveX Display_ActiveY Blank_Color Internal_Hsync_Count Internal_Vsync_Count Horizontal_Y_Offset Horizontal_UV_Offset Vertical_Offset Video_Line_Size Frame_Buffer_Base Video_Line_Mode_Buffer Horizontal_Vertical_Filter Source_X_Offset Horizontal_Video_Scaling Frame_V_Buffer_Compressed_Offset Mb_Width
CS98100
Address B48 B4C B50 B54 B58 B5c B60 B64 B68 B6C B70 B74 B78 B7C C00 C04 C08 C0C C10 C14 C18 C1C C20 C24 C28 C2C C30 C34 C38 C3C Type WO WO WO WO WO WO WO WO WO WO WO WO WO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Function Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Register Name Anti-Flicker Anti-Flicker Anti-Flicker Anti-Flicker Anti-Flicker Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control ENC_Field_at_EAV Subpicture_Color0 Subpicture_Color1 Subpicture_Color2 Subpicture_Color3 Subpicture_Color4 Subpicture_Color5 Subpicture_Color6 Subpicture_Color7 Subpicture_Color8 Subpicture_Color9 Subpicture_Color10 Subpicture_Color11 Subpicture_Color12 Subpicture_Color13 Subpicture_Color14 Subpicture_Color15
Table 13. CS98100 Registers (Continued) 33
CS98100
Address C40 C44 C50 C54 C58 D00 D04 D08 D0C D10 D14 D18 D1C D20 D24 D28 D2C D30 D34 D38 D3C D40 D44 D48 E00 E04 E08 E0C E10 E14 Type R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO Function Subpicture Subpicture Subpicture Subpicture Subpicture On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display PCM PCM PCM PCM PCM PCM Register Name Subpicture_DCI_Address Subpicture_HLI_Address Subpicture_Control Subpicture_Display_Offset Subpicture_Display_Scale OSD_Status OSD_Control OSD_Color_Number OSD_Color_Data OSD_Region1_Control OSD_Region1_Hlimits OSD_Region1_Vlimits OSD_Region1_DramBase OSD_Region2_Control OSD_Region2_Hlimits OSD_Region2_Vlimits OSD_Region2_DramBase OSD_Region3_Control OSD_Region3_Hlimits OSD_Region3_Vlimits OSD_Region3_DramBase OSD_Blend OSD_Debug1 OSD_Debug2 PCM_Run_Clear PCM_Output_Control PCM_Out_FIFO_Start_Address PCM_Out_FIFO_End_Address PCM_Out_FIFO_Interrupt_Address PCM_Out_FIFO_Current_Address
Table 13. CS98100 Registers (Continued) 34
CS98100
Address E18 E20 E24 E28 E2C E30 E34 E38 E3C E40 E44 E48 E4C E50 E58 E5C E60 E64 E68 E6C F00 F04 F40 F44 F48 F4C F50 F54 F58 F5C Type R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W RO R/W RO R/W R/W R/W R/W R/W R/W R/W R/W Function PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM PCM Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Register Name IEC958_Channel_Status PCM_Input_Control PCM_In_FIFO_Start_Address PCM_In_FIFO_End_Address PCM_In_FIFO_Interrupt_Address PCM_Out_FIFO_Interrupt_Address2 PCM_Out_FIFO_Interrupt_Address3 PCM_In_FIFO_Current_Address IEC958_Output_Control IEC958_Output_FIFO_Start_Address IEC958_Output_FIFO_End_Address IEC958_Output_FIFO_Current_Address IEC958_Output_FIFO_Interrupt_Address IEC958_Output_FIFO_Add_Blocks Reserved Reserved User_Data_Start_Frame User_Data_DRAM_Address User_Data_Interrupt_Frame User_Data_Current_Address VidEnc_PowerDown VidEnc_Status Video_Mode Video_Sync Video_Setup Contrast Brigthness Chroma_Saturation Tint VideoDAC_Select
Table 13. CS98100 Registers (Continued) 35
CS98100
Address F60 F64 F68 F6C F70 F74 F78 F7C F80 F84 F88 F8C F90 F94 F98 F9C FA0-FFC 2xxxx Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Function Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder RISC Register Name Test Test Test Burst_Gain Component_Mode Sync_Attenuation Sync_Offset Test Closed_Caption_Control Closed_Caption_Data0 Closed_Caption_Data1 Closed_Caption_Data2 Closed_Caption_Data3 WideScreen_Data0 WideScreen_Data1 WideScreen_Data2 Reserved RISC Processor Registers
Table 13. CS98100 Registers (Continued)
36
CS98100
5. PIN DESCRIPTIONS
.
H_D[15:0] H_CS[3:0] H_A[2:0] H_ALE H_RD H_WR H_RDY M_A[11:0] DR_BS_N M_D[31:0] DR_DQM[3:0] DR_RAS_N DR_CAS_N DR_WE_N DR_AP DR_CKE DR_CKO NVM_CE_N NVM_OE_N NVM_WR_N HSYNC VSYNC CLK27_O VDAT[7:0] Y_G_Y U_B_C V_R_YC RSET COMP VREF AUD_XCK AUD_BCK AUD_LRCK AUD_DO[3:0] IEC958_O AIN_DATA AIN_LRCK
DVD IF / ATAPI IF (27 pins)
Memory IF (58 pins)
Serial DVD (4 pins)
DVDS_CLK DVDS_DAT DVDS_VLD DVDS_SOS XTLCLK_I XTLCLK_O RST_N IR_IN MFG_TST GPIO[7:0] SER_CLK SER_CS SER_DO SER_DI MS_SCL1 MS_SDA1 M_SCL2 M_SDA2
CS98100
Video out (17 pins)
Misc. (13 pins)
Serial I/O (8 pins)
Audio Out (8 pins) Audio In (2 pins)
Figure 14. CS98100 Pin Layout
Table 14 lists the conventions used to identify the pin type and direction.
Symbol I S D U O O4 O8 B B4 B8 Pwr Gnd Name N Name L Description Input Schmitt trigger on input pull down resistor pull up resistor Output Output - 4mA drive Output - 8mA drive Bi-direction Bi-direction - 4mA drive Bi-direction - 8mA drive +2.5V or +3.3V power supply voltage Power supply ground Low active Low active
Table 14. Pin Type and Direction Legend
37
CS98100
6. PIN ASSIGNMENTS
Table 15 lists the pin number, pin name and pin type for the 208-pin CS98100 package. For signal pins, the pin direction after reset is shown. The priPin Name Type Reset Function #1
mary function and pin direction is shown for all signal pins. For some signal pins, a second or third function and direction are also shown.
Dir Function #2 Dir Function #3 Dir Note
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PLL_1V8 M_A11 M_A10 M_A9 M_D8 M_D7 M_D6 IO_GND M_D5 IO_3V3 M_D4 M_D3 M_D2 M_D1 DIG_1V8 M_D0 DR_CKE DIG_GND IO_GND DR_CKO IO_3V3 GPIO1 GPIO2 GPIO3
Pwr O8 O8 O8 B8U B8U B8U Gnd B8U Pwr B8U B8U B8U B8U Pwr B8U B8 Gnd Gnd O8 Pwr B4U B4U B4U I I I O I O I I I I I O O O I I I
PLL Power DR_Addr[11] DR_Addr[10] DR_Addr[9] DR_Data[8] DR_Data[7] DR_Data[6] I/O Ground DR_Data[5] I/O Power DR_Data[4] DR_Data[3] DR_Data[2] DR_Data[1] Core Power DR_Data[0] DR_CKE Core Ground I/O Ground DR_CKO I/O Power GPIO[1] GPIO[2] GPIO[3] B B B 1 1 1 O B O NVM_Data[0] B B B B B NVM_Data[4] NVM_Data[3] NVM_Data[2] NVM_Data[1] B B B B B NVM_Data[5] B O O O B B B NVM_Addr[11] NVM_Addr[10] NVM_Addr[9] NVM_Data[8] NVM_Data[7] NVM_Data[6] O O O B B B
Table 15. Pin Assignments
38
CS98100
Pin Name Type Reset Function #1 Dir Function #2 Dir Function #3 Dir Note
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
GPIO4 GPIO5 Not used Not used Not used Not used Not used Not used Not used Not used M_BS_N DIG_1V8 DR_AP DIG_GND IO_GND DR_RAS_N IO_3V3 DR_CAS_N M_D31 M_D30 M_D29 M_D28 M_D27 IO_GND M_D26 IO_3V3 M_D25
B4U B4U
I I
GPIO[4] GPIO[5]
B B
1 1 2 2 2 2 2 2 2 2
O8 Pwr O8 Gnd Gnd O8 Pwr O8 B8U B8U B8U B8U B8U Gnd B8U Pwr B8U
O
DR_BS_N Core Power
O
O
DR_AP Core Ground I/O Ground
O
O
DR_RAS_N I/O Power
O
O I I I I I
DR_CAS_N DR_Data[31] DR_Data[30] DR_Data[29] DR_Data[28] DR_Data[27] I/O Ground
O B B B B B NVM_Addr[23] O 3 3 3 3 3
I
DR_Data[26] I/O Power
B
NVM_Addr[22]
O
3
I
DR_Data[23]
B
NVM_Addr[21]
O
3
Table 15. Pin Assignments (Continued)
39
CS98100
Pin Name Type Reset Function #1 Dir Function #2 Dir Function #3 Dir Note
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
M_D24 M_D23 M_D22 M_D21 GPIO6 GPIO7 IO_GND NVM_CE_N NVM_OE_N NVM_WE_N IO_3V3 M_D20 M_D19 M_D18 H_A2 H_A1 H_A0 H_ALE M_D17 IO_GND M_D16 M_D15 M_D14 IO_3V3 M_D13 M_D12 M_D11
B8U B8U B8U B8U B4U B4U Gnd O4 O4 O4 Pwr B8U B8U B8U B4 B4 B4 B4U B8U Gnd B8U B8U B8U Pwr B8U B8U B8U
I I I I I I
DR_Data[24] DR_Data[23] DR_Data[22] DR_Data[21] GPIO[6] GPIO[7] I/O Ground
B B B B B B
NVM_Addr[20] NVM_Addr[19] NVM_Addr[18] NVM_Addr[17]
O O O O
3 3 3 3 1 1
O O O
NVM_CE_N NVM_OE_N NVM_WE_N I/O Power
O O O
I I I I I I I I
DR_Data[20] DR_Data[19] DR_Data[18] Hst_Addr[2] Hst_Addr[1] Hst_Addr[0] Hst_ALE DR_Data[17] I/O Ground
B B B O O O O B
NVM_Addr[16] NVM_Addr[15] NVM_Addr[14] GPIO_D[25] GPIO_D{[24] GPIO_D[23] GPIO_D[26] NVM_Addr[13]
O O O B B B B O
3 3 3
3
I I I
DR_Data[16] DR_Data[15] DR_Data[14] I/O Power
B B B
NVM_Addr[12] NVM_Data[15] NVM_Data[14]
O B B
3
I I I
DR_Data[13] DR_Data[12] DR_Data[11]
B B B
NVM_Data[13] NVM_Data[12] NVM_Data[11]
B B B
Table 15. Pin Assignments (Continued)
40
CS98100
Pin Name Type Reset Function #1 Dir Function #2 Dir Function #3 Dir Note
79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
DIG_1V8 M_D10 DIG_GND IO_GND M_D9 M_A8 M_A7 IO_3V3 H_D3 H_D2 H_D1 H_D0 H_CS3 H_CS2 H_CS1 H_CS0 IO_GND M_A6 M_A5 M_A4 IO_3V3 M_A3 M_A2 M_A1 M_A0 IO_GND VDAT0
Pwr B8U Gnd Gnd B8U O8 O8 Pwr B4 B4 B4 B4 B4 B4 B4 B4 Gnd O8 O8 O8 Pwr O8 O8 O8 O8 Gnd B4 O O O O O O O O I I I I I I I I I O O I
Core Power DR_Data[10] Core Ground I/O Ground DR_Data[9] DR_Addr[8] DR_Addr[7] I/O Power Hst_Data[3] Hst_Data[2] Hst_Data[1] Hst_Data[0] Hst_CS[3] Hst_CS[2] Hst_CS[1] Hst_CS[0] I/O Ground DR_Addr[6] DR_Addr[5] DR_Addr[4] I/O Power DR_Addr[3] DR_Addr[2] DR_Addr[1] DR_Addr[0] I/O Ground Vid_Data[0] O GPIO_2[0] B O O O O NVM_Addr[3] NVM_Addr[2] NVM_Addr[1] NVM_Addr[0] O O O O O O O NVM_Addr[6] NVM_Addr[5] NVM_Addr[4] O O O B B B B O O O O GPIO_D[3] GPIO_D[2] GPIO_D[1] GPIO_D[0] GPIO_D[21] GPIO_D[20] GPIO_D[19] GPIO_D[18] B B B B B B B B DVD_Error DVD_SOS I I DVD_Data[3] DVD_Data[2] DVD_Data[1] DVD_Data[0] I I I I B O O NVM_Data[9] NVM_Addr[8] NVM_Addr[7] B O O B NVM_Data[10] B
Table 15. Pin Assignments (Continued)
41
CS98100
Pin Name Type Reset Function #1 Dir Function #2 Dir Function #3 Dir Note
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
VDAT1 VDAT2 VDAT3 VDAT4 VDAT5 VDAT6 VDAT7 HSYNC VSYNC SER_RDY IO_3V3 SER_DO SER_DI SER_CLK AUD_XCK AUD_BCK AUD_LRCK H_WR H_RD MFG_TEST IO_GND DIG_GND AUD_DO0 DIG_1V8 AUD_DO1 AUD_DO2 AUD_DO3
B4 B4 B4 B4 B4 B4 B4 O8 O8 B4U Pwr B4U B4U B4U B4U B4U O4 B4 B4 I Gnd Gnd B4 Pwr B4U B4U B4U
O O O O O O O O O I
Vid_Data[1] Vid_Data[2] Vid_Data[3] Vid_Data[4] Vid_Data[5] Vid_Data[6] Vid_Data[7] Vid_Hsync Vid_Vsync SER_CS I/O Power
O O O O O O O O O B
GPIO_2[1] GPIO_2[2] GPIO_2[3] GPIO_2[4] GPIO_2[5] GPIO_2[6] GPIO_2[7]
B B B B B B B
GPIO_2[8]
B
I I I I O O I I I
SER_Dout SER_Din SER_Clock AUD_XCK AUD_BCK AUD_LRCK Hst_Write Hst_Read (Tie to ground) I/O Ground Core Ground
B B B B O O O O I
GPIO_2[9] GPIO_2[10] GPIO_2[11]
B B B
GPIO_2[12]
GPIO_D[17] GPIO_D[16]
B B
DVD_ENA DVD_RDY
I O
O
AUD_Dout[0] Core Power
O
O O O
AUD_Dout[1] AUD_Dout[2] AUD_Dout[3]
O O O
GPIO_2[13] GPIO_2[14] GPIO_2[15]
B B B
Table 15. Pin Assignments (Continued)
42
CS98100
Pin Name Type Reset Function #1 Dir Function #2 Dir Function #3 Dir Note
133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159
Not used AIN_DATA Not used AIN_LRCK IEC958_O GPIO0 MS_SCL1 MS_SDA1 IO_3V3 M_SCL2 M_SDA2 DVDS_CLK DVDS_DAT DVDS_VLD DVDS_SOS CLK27_O Not used Not used Not used IR_IN IO_GND RST_N Not used PLL_1V8 PLL_GND H_RDY DIG_GND Pwr Gnd B4S Gnd I PLL Power PLL Ground Hst_Ready Core Ground O GPIO_D[22] B DVD_STB I IS Gnd IS I I Infrared I/O Ground Reset_L I I B4U O4 B4U B4SU B4SU Pwr B4SU B4SU IU B4U B4U B4U B4U I I I I I I O I O I I I AIN_LRCK AUD_IEC958 GPIO[0] M_SCL2 M_SDA2 I/O Power M_CLK2 M_DAT2 DVDS_CLK DVDS_DAT DVDS_VLD DVDS_SOS Vid_Clock B B I I B B O GPIO_2[23] GPIO_2[25] GPIO_2[24] GPIO_2[22] B B B B GPIO_2[20] GPIO_2[21] B B I O B B B GPIO_2[18] GPIO_2[19] B B GPIO_2[17] B B4U I AIN_DATA I GPIO_2[16] B I
2
2
1
2 2 2
2
Table 15. Pin Assignments (Continued)
43
CS98100
Pin Name Type Reset Function #1 Dir Function #2 Dir Function #3 Dir Note
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186
H_D15 DIG_1V8 H_D14 H_D13 H_D12 H_D11 H_D10 H_D9 H_D8 IO_3V3 H_D7 H_D6 H_D5 H_D4 Not used Not used Not used Not used DAC_GND DAC_1V8 DAC_DGND U_B_C DAC_3V3 DAC_GND Y_G_Y DAC_3V3 DAC_GND
B4 Pwr B4 B4S B4 B4 B4 B4 B4 Pwr B4 B4 B4 B4
I
Hst_Data[15] Core Power
B
GPIO_D[15]
B
CD_DATA
I
I I I I I I I
Hst_Data[14] Hst_Data[13] Hst_Data[12] Hst_Data[11] Hst_Data[10] Hst_Data[9] Hst_Data[8] I/O Power
B B B B B B B
GPIO_D[14] GPIO_D[13] GPIO_D[12] GPIO_D[11] GPIO_D[10] GPIO_D[9] GPIO_D[8]
B B B B B B B
CD_LRCK CD_BCLK CD_C2P0 DVDL_DI DVDL_DO DVDL_RDY DVDL_CK
I I I I O I O
I I I I
Hst_Data[7] Hst_Data[6] Hst_Data[5] Hst_Data[4]
B B B B
GPIO_D[8] GPIO_D[8] GPIO_D[8] GPIO_D[8]
B B B B
DVD_Data[7] DVD_Data[6] DVD_Data[5] DVD_Data[4]
I I I I 2 2 2 2
Gnd Pwr Gnd Analog Pwr Gnd Analog Pwr Gnd
Analog Ground Digital Power Digital Ground Video Out Analog Power Analog Ground Video Out Analog Power Analog Ground O O
Table 15. Pin Assignments (Continued)
44
CS98100
Pin Name Type Reset Function #1 Dir Function #2 Dir Function #3 Dir Note
187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
V_R_YC DAC_3V3 DAC_GND COMP RSET VREF DAC_3V3 DAC_GND DAC_GND DAC_3V3 DAC_3V3 IO_GND DR_WE_N DR_DQM0 DR_DQM1 DR_DQM2 DR_DQM3 IO_3V3 XTLCLK_I XTLCLK_O IO_GND PLL_GND
Analog Pwr Gnd Analog Analog Analog Pwr Gnd Gnd Pwr Pwr. Gnd O8 O8 O8 O8 O8 Pwr I O Gnd Gnd I O O O O O O
Video Analog Power Analog Ground Compensation Current Set Voltage Ref Analog Power Analog Ground Analog Ground Analog Power Analog Power I/O Ground DR_WE_N DR_DQM[0] DR_DQM[1] DR_DQM[2] DR_DQM[3] I/O Power 27 MHz Osc. 27 MHz Osc. I/O Ground PLL Ground
O
O B B
O O O O O
I O
Table 15. Pin Assignments (Continued) Note 1: Pin may be used for micro-less DVD loader interface Note 2: Pin should be left unconnected Note 3 M_D[31:16] are driving when CS98100 is reading ROM/NVRAM on M_D[15:0], which occurs immediately after reset.
45
CS98100
6.1 Miscellaneous Pins These pins are used for used for basic functions, such as clocking, reset, and infrared receiver interface.
Pin 152 205 206 154 125 Signal Name IR_IN XTLCLK_I XTLCLK_O RST_N MFG_TEST Type I I O I I Description De-modulated infrared Input, from IR receiver. 27 MHz crystal input, or 27 MHz oscillator input 27 MHz crystal output Reset Input, active low. Manufacturing test pin, should always connect to ground.
Table 16. Miscellaneous Interface Pins
46
CS98100
6.2 Serial Interface There are two 2-wire serial controllers, which support industry standard protocols. One controller is a combination master/slave, and is typically used for debug (slave), or to control a small non-volatile memory (master). The slave chip select address is programmable and defaults to a 7-bit value of 0x1A. The second 2-wire controller is a dedicated master and can be used for controlling certain DVD
Pin 139 140 142 143 119 117 118 115 Signal Name MS_SCL1 MS_SDA1 M_SCL2 M_SDA2 SER_CLK SER_DO SER_DI SER_CS Type B B B B B B B B
devices. A third serial controller in the device supports industry standard 3-wire and 4-wire protocols. In master mode, this interface can control a front panel or a small non-volatile memory. In slave mode, it can operate under control of an external processor, for example, in a combination unit.
Description Clock for 2-wire serial port #1 (master/slave port) Data for 2-wire serial port #1 (master/slave port) Clock for 2-wire serial port #2 (master) Data for 2-wire serial port #2 (master) Clock for 4-wire serial port (output for master mode, input for slave mode) Output data for 4-wire serial port - may function as bidirectional data in 3-wire mode. Input data for 4-wire serial port Chip select for 4-wire serial port (output for master mode, input for slave mode). Can also be used as bi-directional ready line.
Table 17. Serial Interface Pin Assignments
47
CS98100
6.3 SDRAM Interface These pins are used to interface the CS98100 with external SDRAM of various sizes. Typical configurations are two 1 Mbyte x16-bit, or one 2 Mbyte
Pin 43, 44, 45, 46, 47, 49, 51, 52, 53, 54, 55, 63, 64, 65, 70, 72, 73, 74, 76, 77, 78, 80, 83, 5, 6, 7, 9, 11, 12, 13, 14, 16 2, 3, 4, 84, 85, 96, 97, 98, 100,101,102, 103 20 17 35 37 40 42 199 203,202,201,200 Signal Name M_D[31:0] Type B
x32-bit. Table 18 gives instructions on how to interface any particular configuration of SDRAM.
Description Memory Data Bus. CS98100 can use all 32 bits or can use only M_D[15:0], in which case M_D[31:16] can be left unconnected.note: 32 bits wide is recommended
M_A[11.0]
O
Memory Address Bus. Connect in order starting with M_A[0] to all RAM address pins not already connected to DR_BS_N or DR_AP. Memory Clock Memory Clock Enable Bank Selection. Always connect to RAM BS or BS0 pin. Memory Auto Pre-charge. Always connect to RAM AP pin. Memory Row Address Strobe Memory Column Address Strobe Memory Write Enable IO Mask of Data Bus DR_DQM[3] -> DR_Data[31:24]
DR_CKO DR_CKE DR_BS_N DR_AP DR_RAS_N DR_CAS_N DR_WE_N DR_DQM[3..0]
O O O O O O O O
Table 18. SDRAM Interface Pin Assignments
48
CS98100
6.4 ROM/NVRAM Interface This interface connects to the non-volatile memory that contains the firmware. The memory could be ROM, NVRAM (FLASH), EEPROM, or any combination of these. This interface can also connect to SRAM that can emulate a ROM on a development system. The bus width is 8 or 16 bits. Most of these
Pin 73, 74, 76, 77, 78, 80, 83, 5, 6, 7, 9, 11, 12, 13, 14. 16 28 47, 49, 51, 52, 53, 54, 55, 63, 64, 65, 70, 72 59 60 43 61 Signal Name M_D[15:0] Type B
pins are shared with the DRAM interface, which operates simultaneously with the ROM/NVRAM interface.
Description NVM_Data[15:0], Memory Data Bus (shared with bits [15:0] of DRAM data bus). Use M_D[7:0] for 8-bit interface. NVM_Addr[11:0], Memory Address Bus[11:0] (shared with DRAM address bus) NVM_Addr[23:12], Memory Address Bus[23:12] (shared with bits [27:16] of DRAM data bus) ROM/NVRAM Chip Enable. ROM/NVRAM Output Enable. Copy of ROM/NVRAM Output Enable. NVRAM Write Enable.
M_A[11:0] M_D[27:16]
O O
NVM_CE_N NVM_OE_N M_D[31] NVM_WE_N
O O O O
Table 19. ROM/NVRAM Interface Pin Assignments
49
CS98100
6.5 Digital Video Output Interface This interface can be used to drive CCIR601/CCIR-656 digital data to an external video encoder (such as an CS4955), for example if a fourth DAC is required. The CS98100 is sync master of
this interface. For progressive mode, the data pins output on both edges of the clock. Optionally, this interface can be used only to generate separate or combined horizontal/ vertical sync, for example to drive syncs to a VGA monitor.
Description
Pin 113 114 148 112, 111, 110, 109, 108, 107, 106, 105
Signal Name HSYNC VSYNC CLK27_O VDAT[7:0]
Type O O O O Horizontal Sync output
Vertical or combined vertical/horizontal Sync output 27 MHz Clock Output. Video Data Output[7:0] in YCrCb format.
Table 20. Video Output Interface Pin Assignments
50
CS98100
6.6 Audio Output/Input Interface This is the audio PCM interface that connects to an audio CODEC. The sample rate and the size of the
samples are programmable for both input and output direction.
Pin 120 121 122 128 130 131 132 137 134 136
Signal Name AUD_XCK AUD_BCK AUD_LRCK AUD_DO0 AUD_DO1 AUD_DO2 AUD_DO3 IEC958_O AIN_DATA AIN_LRCK
Type B O O O O O O O I I
Description Audio 256x/384x Clock input or output to Serial DAC. When output, it's generated from CS98100 internal PLL. Audio Bit Clock output to serial DAC. Polarity is programmable. Audio Out Left/Right Clock to serial DAC. Audio Serial PCM Data Out[0] (Front) Audio Serial PCM Data Out[1] (Surround) Audio Serial PCM Data Out[2] (Center + LFE) Audio Serial PCM Data Out[3] (2-channel downmix) IEC-958 Output This input can come from from an external comparator. Left/Right Clock. Input from external audio ADC. The CS98100 can be programmed to use the Audio Output function's internally generated LR clock, in which case this pin is not required.
Table 21. Audio Output Interface Pin Assignments
51
CS98100
6.7 Host Master/ATAPI Interface This 16-bit parallel host interface allows the CS98100 to be a host master, controlling other devices that would be used on the same system. The interface supports a programmable protocols and speeds, including multiplexed and non-multiplexed addressing. Slaves with different protocols can be connected at the same time, controlled by different
Pin 91, 92, 93, 94 69 124 123 158 66, 67, 68 160, 162, 163, 164, 165, 166, 167, 168, 170, 171, 172, 173, 87, 88, 89, 90 Signal Name H_CS[3:0] H_ALE H_RD H_WR H_RDY H_A[2:0] H_D[15:0] Type O O O O I O B
chip selects. For example, two chip selects can be used to control an ATAPI DVD device, while the other two chip selects can control another ATAPI or non-ATAPI slave device.
Description Host Chip Select[3:0]. The host master can be programmed to use a different protocol for each of the 4 chip selects Host address latch enable. Used for modes which multiplex upper address information onto the data lines Host Read Request. Host Write Request. Host Ready. Connect to pull-up or pull-down if host is not used. Host Address[2:0]. Host Data Bus[15:0]. These pins can also output Host Address during the address phase for multiplexed address/data mode. Tie together to pull-up or pull-down if host is not used.
Table 22. Host Master Interface Pin Assignments
52
CS98100
6.8 DVD I/O Channel Interface This interface connects to standard DVD loaders, and consists of three parts: Control, DVD Data and CD Data. This interface shares CS98100 pins with the Host Master/ATAPI interface. The pin definiPin 94 93 124 123 158 170, 171, 172, 173, 87, 88, 89, 90 164 163 162 160 168 167 166 165 Signal Name DVD_SOS DVD_Error H_RD H_WR H_RDY H_D[7:0] CD_C2P0 CD_BCLK CD_LRCK CD_DATA DVDL_CK DVDL_RD Y DVDL_DO DVDL_DI Type I I O I I I I I I I O I O I
tion is set via register programming, and the two modes are mutually exclusive.
Description DVD data start sector signal from loader DVD data error signal from loader DVD_RDY, DVD data ready signal to loader DVD_ENA, DVD data enable signal from loader DVD_STB, DVD data clock from loader DVD_Data[7:0], DVD data port parallel data input from loader CD error signal from loader CD clock from loader CD left/right clock from loader CD serial data from loader Control port clock to loader Control port ready signal from loader Control port serial command to loader Control port serial status from loader
Table 23. DVD I/O Channel Interface Pin Assignments
53
CS98100
6.9 DVD Serial Data Interface This interface connects to the data port of low cost DVD loaders using a 4-wire serial interface. In this case, control for the loader will typically be done using the 2-wire serial interface master. The ATAPI/IO channel pins are then free to be used for a
Pin 144 145 146 147 Signal Name DVDS_CLK DVDS_DAT DVDS_VLD DVDS_SOS Type I I I I
second DVD loader, a general purpose ATAPI, or as GPIOs.
Description DVD clock input - rising edge is the active edge DVD serial data input (data can be input MSB or LSB first) DVD valid - a bit of data is clocked in when this pin is high DVD start of sector input - active high
Table 24. DVD Serial Data Interface Pin Assignments
54
CS98100
6.10 Video Encoder Interface The video encoder interface has three DAC outputs, and operates in one of three modes: component YUV, component RGB, and S-Video plus composite. The component modes may operate eiPin 181 184 187 190 191 192 Signal Name U_B_C Y_G_Y V_R_YC COMP RSET VREF Type O O O O B B
ther normal interlaced resolution, or progressive (high resolution).
Description Analog video output - U(YUV), B(RGB), C(Y/C/YC) Analog video output - Y(YUV), G(RGB), Y(Y/C/YC) Analog video output - V(YUV), R(RGB), YC(Y/C/YC) Compensation pin, should be connect through 0.1F capacitor to analog 3.3V supply Current adjust pin, connect through 174,1% resistor to analog ground Voltage reference pin, connect through 0.1F capacitor to analog ground
Table 25. Video Encoder Interface Pin Assignments
55
CS98100
6.11 General Purpose Input/Output (GPIO) The CS98100 provides a number of GPIO pins, each with individual output three-state controls. There are eight dedicated GPIO pins, which can also be used to generate internal interrupts based on edge or level events on the pins. Two groups of adPin 57, 56, 26, 25, 24, 23, 22, 138 Signal Name GPIO[7:0] Type B B
ditional pins may also be re-defined as GPIOs if not required for other functions. Each of these additional pins has its own control register bit to select either GPIO or normal function for the pin.
Description 8 General purpose I/O on dedicated pins 28 General purpose I/Os, redefined from following pins: DVDS_VLD, DVDS_SOS, DVDS_DAT, CLK27_O, SDA2, SCL2, SDA1, SCL1, AIN_LRCK, AIN_DATA, AUD_DO_3, AUD_DO_2, AUD_DO_1, AUD_BCK, SER_CLK, SER_DI, SER_DO, SER_RDY, VDAT_7, VDAT_6, VDAT_5, VDAT_4, VDAT_3, VDAT_2, VDAT_1, VDAT_0
146, 147, 145, 148, 143, 142, 140, GPIO_2[2 139, 136, 134, 132, 5:24] 131, 130, 121, 119, GPIO_2[2 118, 117, 115, 112, 3:20] 111, 110, 109, 108, GPIO_2[1 9:16] 107, 106, 105 GPIO_2[1 5:12] GPIO_2[1 1:8] GPIO_2[7: 4] GPIO_2[3: 0] 69, 66, 67, 68, 158, 91, 92, 94, 123, 124, 162, 163, 164, 166, 167, 168, 171, 172, 173, 88, 89, 90 93, 160, 165, 170, 87, GPIO_D[2 6:24] GPIO_D[2 3:20] GPIO_D[1 9:16] GPIO_D[1 5:12] GPIO_D[1 1:8] GPIO_D[7: 4] GPIO_D[3: 0]
B
27 General purpose I/Os, redefined from following pins: H_ALE, H_A_2, H_A_1, H_A_0, H_RDY, H_CS_3,H_CS_2, H_CS_1, H_CS_0, H_WR, H_RD, H_D_15, H_D_14, H_D_13, H_D_12, H_D_11, H_D_10, H_D_9, H_D_8, H_D_7, H_D_6, H_D_5, H_D_4, H_D_3, H_D_2, H_D_1, H_D_0
Table 26. General Purpose I/O Interface Pin Assignments
56
CS98100
6.12 Power and Ground The CS98100 requires five different types of power supplies for the Plus, internal logic, IO pins, video DAC-digital and video DAC analog. The PLLs, internal logic and video DAC digital use 1.8 V supply voltage. The IO pins and video DAC analog use 3.3 V supply voltage. It is recommended to use good
Pin 1, 156 157, 208 15, 36, 79, 129, 161 18, 38, 81, 127, 159 10, 21, 41, 50, 62, 75, 86, 99, 116, 141, 169, 204 8, 19, 39, 48, 58, 71, 82, 95, 104, 126, 153, 198, 207 179 180 182, 185, 188, 193, 196, 197 178, 183, 186, 189, 194, 195 Signal Name PLL_1V8 PLL_GND DIG_1V8 DIG_GND IO_3V3 Type 1.8V for internal PLLs Ground for internal PLLs 1.8V for internal core logic Ground for internal core logic 3.3V for Digital I/Os
layout techniques to provide isolation between the supply types on the board. Contact Cirrus Logic applications engineering for layout guidelines.
Description
IO_GND
Ground for Digital I/Os
DAC_1V8 DAC_DGND DAC_3V3 DAC_GND
Digital 1.8V for video DAC Digital ground for video DAC Analog 3.3V for video DAC Analog ground for video DAC Table 27. Power and Ground
57
CS98100
7. 208 PIN MQFP PACKAGE SPECIFICATIONS
30.600.30 28.000.13
3.68(MAX) 3.23 0.08 0.10(MIN)
157 156
208 1
52 53 104
105
30.600.30
28.000.13
0.500.10
Detail A
0.15
+0.10 -0.05 WITH PLATING BASE METAL 0.20 0.05 1.300.20
0~10
0.500.20
DETAIL A
Notes: Measurement Unit = mm Figure 15. CS98100 208-Pin MQFP Package Drawing
58
* Notes *

▲Up To Search▲

Price & Availability of CS98100

	To Download CS98100 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .